Creation of certain integrated circuit packages and printed circuit boards often uses an electro-plating manufacturing process. One physical artifact of the electroplating process is one or more stub traces that electrically connect a signal via to a perimeter of the package. In view of the sensitivity of some of the signaling frequencies, some integrated circuit packages are designed to connect to controlled impedance transmission lines. At frequencies above 500 MHz, the stub trace presents a transmission impedance mismatch that affects signal integrity. The adverse impact of the resulting signal degradation increases with the signal frequency.
As a signal travels down a signal trace and encounters a via in parallel with the stub trace, the signal splits with a first portion traveling along the via and a second portion traveling along the stub trace. As the second portion of the signal encounters an end of the stub trace, it is reflected. The reflected signal then mixes with the original signal at the via, and causes signal degradation. A relatively short stub trace will reflect the second signal and cause signal degradation early on in a signal transition. This may not present as much a problem if signal registration is later on in the signal transition and after the area in the signal that mixes with the reflection. Longer stub traces, therefore, present more of a problem because reflected signals are more likely to disturb the signal at the via at a time when another component of the system registers the signal.
One available solution to the foregoing problem in the art is the use of an electroless plating or printing process. Printed circuit boards that use a printing process do not have the stub trace artifacts. IC packages, however, are typically manufactured using either the electroplating process or the electroless plating process. The electroless plating process does not create stub traces as an artifact of manufacturing, and therefore, does not present the same issue. Unfortunately, the electroless plating process has higher variability in conductor geometry making it difficult if not impossible to carefully control signal trace impedance. For high frequency signal traces, however, the uniformity of conductor geometry is an important factor in maintaining signal quality. Accordingly, the benefit of the absence of stub traces is somewhat offset by the variability in signal trace geometry. The electro-less plating process, therefore, only partially addresses the issue of obtaining high frequency signal quality. In addition, not all IC package styles are available in the electroless plating process. Accordingly, the electroless plating process may not be available or advisable in certain IC package applications.
Another solution is to arrange the IC die so that all of the contacts carrying high-speed signals are placed on a perimeter of the die where the stub traces are shortest. It saves costs, however, to manufacture small ICs with high density and higher density ICs dictate that interior contacts also carry the high-speed signals.
There remains a need, therefore, to address the deleterious affects of the stub traces that are an artifact of the electro-plating manufacturing process.